Modern electronic devices, especially semiconductor (SC) devices and integrated circuits (ICs) are at risk of damage due to electrostatic discharge (ESD) events. It is well known that electrostatic discharge from handling SC devices and ICs, by humans or machines or both, is a source of such excess voltage. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input/output (I/O) and other terminals of such SC devices and IC's. FIG. 1 is a simplified schematic diagram of circuit 10 wherein ESD clamp 11 is placed between input/output (I/O) terminals 22 and ground or common terminal 23 of a SC device or IC to protect the other devices on the chip, that is, to protect circuit core 24 which is also coupled to I/O terminals 22 and common (e.g., “GND”) terminal 23. Zener diode symbol 11′ within ESD clamp 11 indicates that the function of ESD clamp 11 is to limit the voltage than can appear across circuit core 24 irrespective of the voltage applied to external I/O and GND terminals 22, 23. As used herein, the abbreviation “GND” is intended to refer to the common or reference terminal of a particular circuit or electronic element, irrespective of whether it is actually coupled to an earth return, and the abbreviation “I/O” is intended to include any external terminals other than “GND”.
FIG. 2 is a simplified schematic diagram illustrating internal components of prior art ESD clamp 21 which is inserted in circuit 10 in place of ESD clamp 11. ESD clamp 21 comprises bipolar transistor 25, having emitter 26, collector 27 and base 28, resistance 19 and Zener diode 130 having terminals 131, 132. Zener diode 130 can also exhibit some small inherent resistance. Resistance 19 can include any inherent contact resistance and the effect of the inherent base resistance (not shown). In applications employing Zener diode 130 it is common to directly connect the base and emitter contacts, in which case resistance 19 is small. The purpose of resistance 19 in ESD clamp 21 is not to provide triggering, since this is provided by Zener diode 130 but to keep base 28 and emitter 26 at substantially the same potential unless there is an ESD event, so that in normal operation of circuit 10, ESD clamp 21 does not interfere with the operation of circuit core 24. When the voltage across terminals 22, 23 rises beyond a predetermined limit, Zener diode 130 turns on, thereby switching bipolar transistor 25 into conduction and desirably clamping the voltage across terminals 22, 23 at a level below a value capable of damaging circuit core 24.
FIG. 3 is a simplified schematic diagram illustrating internal components of prior art ESD clamp 31 which is inserted in circuit 10 in place of ESD clamp 11. ESD clamp 31 comprises bipolar transistor 25, having emitter 26, collector 27 and base 28 and resistor 29. Resistor 29 is generally much larger than the inherent base and contact resistance. Resistor 29 is used to trigger bipolar transistor 25 into conduction when an ESD event occurs. When an ESD event arrives across terminals 22, 23 the collector-base voltage rises very rapidly and a small but finite leakage current begins to flow through the reverse biased collector base junction and through resistor 29. By using a value for resistor 29 that is large compared to the inherent base resistance, sufficient voltage is developed across resistor 29 to bias the emitter-base junction into conduction, thereby turning on transistor 25 and providing ESD protection by clamping the external voltage at a level below that capable of causing damage to circuit core 24. After the ESD transient has passed, resistor 29 discharges any charge stored on the emitter base junction, thereby returning transistor 25 to its non-conductive state so that in normal operation of circuit 10, ESD clamp 31 does not interfere with the operation of circuit core 24.
Design, construction and operation of such ESD devices is described for example in commonly owned U.S. Pat. No. 7,164,566 B2 “Electrostatic Discharge Protection Device and Method Therefore” by Hongzhong Xu et al, and further described by Danielle Coffing and Richard Ida in “Analysis of a Zener-Triggered Bipolar ESD Structure in a BiCMOS Technology”, IEEE BC™ 1998, pages 31-34, and by Joshi, Ida, Givelin and Rosenbaum in “An Analysis of Bipolar Breakdown and its Application to the Design of ESD Protection Circuits”, IEEE 01CH37167, 39th Annual International Reliability Physics Symposium, Orlando, Fla., 2001, pages 240-245. FIG. 4 is an illustration of a typical current-voltage characteristic of an ESD clamp, where voltage Vt1 is referred to as the trigger voltage and voltage Vh is referred to as the holding voltage.